Transmitter circuit, transmission circuit and driver unit

ABSTRACT

A transmitter circuit for use in a display device of the type having a transmission line consisting of aluminum or copper conductor formed on a glass substrate includes a driver circuit, which has a non-inverting output terminal and an inverting output terminal, for outputting a signal current, which has a loop direction that changes based upon an input signal, to the non-inverting and inverting output terminals; and an output-waveform control circuit for detecting the edge of the waveform of the input signal and responding by increasing the signal current temporarily.

FIELD OF THE INVENTION

[0001] This invention relates to a transmitter circuit, a transmissioncircuit and a driver unit. More particularly, the invention relates to atransmitter circuit, a transmission circuit and a driver unit applicableto a liquid crystal display device, an organic electroluminescencedisplay device and a plasma display device.

BACKGROUND OF THE INVENTION

[0002] Conventionally, in a matrix-type liquid crystal display device,an organic electroluminescence (EL) display device and a plasma displaydevice, a timing controller LSI chip, which successively generates andoutputs one horizontal line of a grayscale data signal and scanningsignal from one frame of image signals, and a source driver LSI chip,which serves as a driver unit that receive the grayscale data signal anddrive respective ones of data lines of a display panel, are mounted on aprinted circuit board. Transmission of signals between the timingcontroller LSI chip and the source driver LSI chip, as well astransmission of signals between the source driver LSI chips that arecascade-connected, is achieved by transmission lines consisting ofprinted conductor. An LVDS (Low Voltage Differential Signaling)interface, for example, is a high-speed interface used as thetransmission circuit.

[0003] As shown in FIG. 11, the conventional transmitter circuit of anLVDS interface includes a constant-current source 6 having one endconnected to a high-potential power supply VDD; a constant-currentsource 7 having one end connected to a low-potential power supply VSS;an N-channel MOS transistor N1 and an N-channel MOS transistor N2serving as switching means connected serially between the other end ofthe constant-current source 6 and the other end of the constant-currentsource 7; an N-channel MOS transistor N3 and an N-channel MOS transistorN4 serving as switching means connected serially between the other endof the constant-current source 6 and the other end of theconstant-current source 7; a non-inverting output terminal 2 connectedto the node of the N-channel MOS transistor N1 and N-channel MOStransistor N2; and an inverting output terminal 3 connected to the nodeof the N-channel MOS transistor N3 and N-channel MOS transistor N4. Aterminating resistor of a receiver circuit is connected between thenon-inverting output terminal 2 and inverting output terminal 3 via apair of transmission lines, and a voltage comparator of the receivercircuit recognizes signal logic by discriminating the voltage across theterminating resistor. A CMOS-level non-inverted input data signalsupplied to an input terminal 1 is applied to the gate terminal of theN-channel MOS transistor N1 and to the gate terminal of the N-channelMOS transistor N4. An inverting input data signal, which is a result ofthe non-inverted input data signal being inverted by the CMOS-typeinverter circuit 5, is applied to the gate terminal of the N-channel MOStransistor N2 and to the gate terminal of the N-channel MOS transistorN3. When the non-inverted input data signal is at the VDD level servingas logic H, the N-channel MOS transistors N1 and N4 turn on, theN-channel MOS transistors N2 and N3 turn off, loop signal current flowsfrom the constant-current source 6 to the constant-current source 7 viathe N-channel MOS transistor N1, non-inverting output terminal 2,transmission line, terminating resistor, transmission line, invertingoutput terminal 3 and N-channel MOS transistor N4, and the receivercircuit recognizes the logic H level. When the non-inverted input datasignal is at the VSS level serving as logic L, the N-channel MOStransistors N1 and N4 turn off, the N-channel MOS transistors N2 and N3turn on, loop signal current in the opposite direction flows from theconstant-current source 6 to the constant-current source 7 via theN-channel MOS transistor N3, non-inverting output terminal 3,transmission line, terminating resistor, transmission line,non-inverting output terminal 2 and N-channel MOS transistor N2, and thereceiver circuit recognizes the logic L level.

[0004] Patent Document 1

[0005] Japanese Patent Kokai Publication No. JP-P2000-31810A (FIG. 13)

SUMMARY OF THE DISCLOSURE

[0006] For the purpose of reducing the size, weight and cost of displaydevices, progress has recently been made in COG (Chip On Glass)techniques for mounting a source driver LSI chip on a glass substratesuch as a matrix display panel. In such an arrangement, transmission ofsignals between a timing controller LSI chip and the source driver LSIchip, as well as transmission of signals between the cascade-connectedsource driver LSI chips, is by transmission lines, which consist ofaluminum or copper conductor, formed on the glass substrate.

[0007] However, whereas the resistance component of a transmission lineconsisting of copper conductor on a printed circuit board is severaltens of milliohms, the resistance component of a transmission lineconsisting of aluminum or copper conductor formed on a glass substrateis several hundred ohms because both the conductor thickness andconductor width are small owing to the fabrication process for thedisplay panel. The output capacitance of the transmitter circuit and theinput capacitance of the receiver circuit is several picofarads.Consequently, even if signal transmission is performed in ahigh-frequency region that exceeds 100 MHz with the higher resolutionsand larger screen areas of display panels, the signal waveform at theinput end of the receiver circuit becomes significantly blunted owing tothe RC time constant and a problem that arises is that good signaltransmission cannot be achieved.

SUMMARY OF THE INVENTION

[0008] Accordingly, an object of the present invention is to provide atransmitter circuit, a transmission circuit and a driver unit in whichhigh-speed signal transmission can be performed by reducing blunting ofthe signal waveform at the input end of the receiver circuit even if thetransmission line has a high resistance component as in the manner ofaluminum or copper conductor on a glass substrate.

[0009] The above and other objects are attained by a transmitter circuitin accordance with one aspect of the present invention, comprising adriver circuit, which has a non-inverting output terminal and aninverting output terminal, for outputting a signal current, whose loopdirection changes based upon an input signal, to the non-invertingoutput terminal and inverting output terminal; and an output-waveformcontrol circuit for detecting a waveform edge of the input signal andincreasing the signal current temporarily.

[0010] Further, in the transmitter circuit in accordance with thepresent invention, the output-waveform control circuit preferablyincludes an edge detecting circuit for outputting a detection signalwhen the edge is detected; switch means turned on by the detectionsignal; and a current source for supplying a current, which is added tothe signal current, when the switch means has been turned on.

[0011] In the transmitter circuit in accordance with another aspect ofthe present invention, the output-waveform control circuit preferablyincludes a first inverter to which a non-inverted input signal isapplied; a first capacitor having one end connected to an outputterminal of the first inverter circuit and another end connected to theinverting output terminal; a second inverter circuit to which aninverted input signal is applied; and a second capacitor having one endconnected to an output terminal of the second inverter circuit andanother end connected to the non-inverting output terminal.

[0012] In the transmitter circuit in accordance with the presentinvention, the driver circuit preferably includes a first transistor,which has a non-inverting output terminal and an inverting outputterminal, to which a non-inverted input signal is applied, for switchingin response and passing a current from a high-potential power supply tothe non-inverting output terminal; a third transistor, to which theinverted input signal is applied, for switching in response and passinga current from the high-potential power supply to the inverting outputterminal; a fourth transistor, to which the non-inverted input signal isapplied, for switching in response and passing a current from theinverting output terminal to a low-potential power supply; and a secondtransistor, to which the inverted input signal is applied, for switchingin response and passing a current from the non-inverting output terminalto the low-potential power supply.

[0013] Further, the above and other objects are attained by atransmitter circuit in accordance with another aspect of the presentinvention, comprising a driver circuit, which has a non-inverting outputterminal and an inverting output terminal, for outputting a differentialvoltage, whose polarity changes based upon an input signal, to thenon-inverting output terminal and inverting output terminal; and anoutput-waveform control circuit for detecting a waveform edge of theinput signal and increasing the differential voltage temporarily.

[0014] Further, the output-waveform control circuit in the transmittercircuit according to the present invention preferably includes an edgedetecting circuit for outputting a first detection signal when a risingedge of the waveform is detected and a second detection signal when afalling edge of the waveform is detected; switch means for pulling upthe non-inverting output terminal in response to the first detectionsignal; switch means for pulling down the inverting output terminal inresponse to the first detection signal; switch means for pulling downthe non-inverting output terminal in response to the second detectionsignal; and switch means for pulling up the inverting output terminal inresponse to the second detection signal.

[0015] Further, the driver circuit according to the present inventionincludes a potential dividing circuit for generating high- and low-levelpotential-divided voltages; switch means for selecting thepotential-divided voltage based upon a non-inverted input signal andoutputting the voltage to the non-inverting output terminal; and switchmeans for selecting the potential-divided voltage based upon thenon-inverted input signal and outputting the voltage to the invertingoutput terminal.

[0016] Further, according to the present invention, the foregoing objectis attained by providing a transmission circuit comprising theabove-described transmitter circuit; a transmission line having one endconnected to the non-inverting output terminal and inverting outputterminal of the transmitter circuit; and a receiver circuit connected tothe other end of the transmission line.

[0017] Further, the above and other objects are attained by a driverunit in accordance with another aspect of the present invention,comprising a shift register circuit to which is input grayscale data fordriving data lines of a matrix display panel; and the above-describedtransmitter circuit connected to a serial output end of the shiftregister circuit.

[0018] The drive unit according to the present invention preferablycomprises the transmission line described above.

[0019] Further, the transmission line of the driver unit according tothe present invention comprises a conductor on a glass substrate of thematrix display panel.

[0020] Still other objects and advantages of the present invention willbecome readily apparent to those skilled in this art from the followingdetailed description in conjunction with the accompanying drawingswherein only the preferred embodiments of the invention are shown anddescribed, simply by way of illustration of the best mode contemplatedof carrying out this invention. As will be realized, the invention iscapable of other and different embodiments, and its several details arecapable of modifications in various obvious respects, all withoutdeparting from the invention. Accordingly, the drawing and descriptionare to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a circuit diagram illustrating a transmitter circuitaccording to a first embodiment of the present invention;

[0022]FIG. 2 is a circuit diagram illustrating a transmission circuithaving the transmitter circuit of the first embodiment;

[0023]FIG. 3 is a diagram useful in describing the operation of thetransmitter circuit of the first embodiment;

[0024]FIG. 4 is a circuit diagram illustrating a transmitter circuitaccording to a second embodiment of the present invention;

[0025]FIG. 5 is a diagram useful in describing the operation of thetransmitter circuit of the second embodiment;

[0026]FIG. 6 is a circuit diagram illustrating a transmitter circuitaccording to a third embodiment of the present invention;

[0027]FIG. 7 is a diagram useful in describing the operation of thetransmitter circuit of the third embodiment;

[0028]FIG. 8 is a circuit diagram illustrating a transmitter circuitaccording to a fourth embodiment of the present invention;

[0029]FIG. 9 is a block diagram of driver units according to a fifthembodiment of the present invention;

[0030]FIG. 10 is a diagram illustrating the structure of a matrixdisplay panel having the driver units of the fifth embodiment; and

[0031]FIG. 11 is a circuit diagram illustrating a transmitter circuitaccording to the prior art.

PREFERRED EMBODIMENTS OF THE INVENTION

[0032] Preferred embodiments of the present invention will now bedescribed in detail with reference to the drawings.

[0033]FIG. 1 is a diagram illustrating a configuration of a transmittercircuit according to a first embodiment of the present invention. Asshown in FIG. 1, the transmitter circuit includes an input terminal 1, anon-inverting output terminal 2, an inverting output terminal 3, adriver circuit 4 and an output-waveform control circuit 8.

[0034] The driver circuit 4 includes a CMOS-type inverter circuit 5, aconstant-current source 6 for signal current source, a constant-currentsource 7 for signal current sink, and N-channel MOS transistors N1, N2,N3 and N4. One end of the constant-current source 6 is connected to ahigh-potential power supply VDD and the other end thereof is connectedto the drain terminal of the N-channel MOS transistor N1 and to thedrain terminal of the N-channel MOS transistor N3. One end of theconstant-current source 7 is connected to a low-potential power supplyVSS and the other end thereof is connected to the source terminal of theN-channel MOS transistor N2 and to the source terminal of N-channel MOStransistor N4. The source terminal of the N-channel MOS transistor N1 isconnected to the drain terminal of the N-channel MOS transistor N2 andthe source terminal of the N-channel MOS transistor N3 is connected tothe drain terminal of the N-channel MOS transistor N4. The inputterminal 1 is connected to the gate terminal of the N-channel MOStransistor N1, the gate terminal of the N-channel MOS transistor N4 andthe input terminal of the inverter circuit 5, and the output terminal ofthe inverter circuit 5 is connected to the gate terminal of theN-channel MOS transistor N2 and to the gate terminal of the N-channelMOS transistor N3. The non-inverting output terminal 2 is connected tothe source terminal of the N-channel MOS transistor N1 and the invertingoutput terminal 3 is connected to the source terminal of the N-channelMOS transistor N3.

[0035] The output-waveform control circuit 8 includes an edge detectingcircuit 9, a constant-current source 12 for a signal current source,switch means 13, a constant-current source 15 for signal current sinkand switch means 16.

[0036] The edge detecting circuit 9 includes a CMOS-type non-invertingbuffer circuit 10 and a CMOS-type exclusive-OR gate 11. The inputterminal of the non-inverting buffer circuit 10 and a first inputterminal of the exclusive-OR gate 11 are tied together and connected tothe input terminal 1 serving as the input terminal of the edge detectingcircuit 9. The output terminal of the non-inverting buffer circuit 10 isconnected to a second input terminal of the exclusive-OR gate 11. Theedge detecting circuit 9 detects the rising and falling edges of thewaveform of a non-inverted input data signal that is supplied to theinput terminal 1 and outputs an edge detection signal EMP from theoutput terminal thereof. The pulse width of the edge detection signalEMP is equal to the delay time of the non-inverting buffer circuit 10,and the delay time can be set appropriately. If the non-inverting buffercircuit 10 is composed by an even-number stages of inverter circuits,then the delay time can be changed by changing the number of stages thatoperate.

[0037] The switch means 13 includes a CMOS-type inverter circuit 14 anda P-channel MOS transistor P1. The source terminal of the P-channel MOStransistor P1 is connected to the high-potential power supply VDD, thedrain terminal of the P-channel MOS transistor P1 is connected to oneend of the constant-current source 12, and the gate terminal of theP-channel MOS transistor P1 is connected to the output terminal of theinverter circuit 14. The input terminal of the inverter circuit 14 isconnected to the output terminal of the exclusive-OR gate 11 serving asthe output terminal of the edge detecting circuit 9. The P-channel MOStransistor P1 is turned on when the edge detection signal EMP at the VDDlevel (the logic H level) is input. The other end of theconstant-current source 12 serially connected to the switch means 13 isconnected to the drain terminal of the N-channel MOS transistor N1 andto the drain terminal of the N-channel MOS transistor N3.

[0038] The source of an N-channel MOS transistor N5 serving as switchmeans 16 is connected to the low-potential power supply VSS, the drainof the N-channel MOS transistor N5 is connected to one end of theconstant-current source 15 and the gate terminal of the N-channel MOStransistor N5 is connected to the output terminal of the exclusive-ORgate 11. The N-channel MOS transistor N5 is turned on when the edgedetection signal EMP at the VDD level (the logic H level) is input. Theother end of the constant-current source 15 serially connected to theswitch means 16 is connected to the source terminal of the N-channel MOStransistor N2 and to the source terminal of the N-channel MOS transistorN4.

[0039]FIG. 2 is a circuit diagram illustrating a transmission circuithaving the transmitter circuit according to this embodiment. As shown inFIG. 2, the transmission circuit includes a transmitter circuit 43according to this embodiment, a balanced transmission line 44, whichcomprises a pair of lines, connected at one end to the non-invertingoutput terminal 2 and to the inverting output terminal 3 of thetransmitter circuit 43, and a receiver circuit 45 connected to the otherend of the transmission line 44. The receiver circuit 45 includes aterminating resistor RL connected to the other end of the transmissionline 44, and a differential-type voltage comparator CMP having anon-inverted input terminal and an inverting input terminal connected torespective ones of the two ends of the terminating resistor RL. Thevoltage comparator CMP recognizes signal logic by discriminating thevoltage across the terminating resistor RL. The transmission line 44,which comprises aluminum or copper conductor on the glass substrate of amatrix display panel, has a high resistance component. The non-invertingoutput terminal 2 has a parasitic capacitance CO1 with respect to thelow-potential power supply VSS, the inverting output terminal 3 aparasitic capacitance CO2 with respect to the low-potential power supplyVSS, the non-inverting terminal of the receiver circuit 45 a parasiticcapacitance CI1 with respect to the low-potential power supply VSS, andthe inverting terminal of the receiver circuit 45 a parasiticcapacitance CI2 with respect to the low-potential power supply VSS.

[0040] With regard to the transmitter circuit 43, the CMOS-levelnon-inverted input data signal that enters the input terminal 1 isapplied to the gate terminal of the N-channel MOS transistor N1 and tothe gate terminal of the N-channel MOS transistor N4. An inverted inputdata signal, which is a result of the non-inverted input data signalbeing inverted by the CMOS-type inverter circuit 5, is applied to thegate terminal of the N-channel MOS transistor N2 and to the gateterminal of the N-channel MOS transistor N3.

[0041] The N-channel MOS transistor N1, in response to input of thenon-inverted input data signal, switches to pass the current from thehigh-potential power supply VDD to the non-inverting output terminal 2;the N-channel MOS transistor N3, in response to input of the invertedinput data signal, switches to pass the current from the high-potentialpower supply VDD to the inverting output terminal 3; the N-channel MOStransistor N4, in response to input of the non-inverted input datasignal, switches to pass the current from the inverting output terminal3 to the low-potential power supply VSS; and the N-channel MOStransistor N2, in response to input of the non-inverted input datasignal, switches to pass the current from the non-inverting outputterminal 2 to the low-potential power supply VSS.

[0042] When the non-inverted input data signal is at the VDD levelserving as logic H, the N-channel MOS transistors N1 and N4 turn on, theN-channel MOS transistors N2 and N3 turn off, loop signal current flowsfrom the constant-current source 6 to the constant-current source 7 viathe N-channel MOS transistor N1, non-inverting output terminal 2,transmission line 44, terminating resistor RL, transmission line 44,inverting output terminal 3 and N-channel MOS transistor N4, and thereceiver circuit 45 recognizes the logic H level.

[0043] When the non-inverted input data signal is at the VSS levelserving as logic L, the N-channel MOS transistors N1 and N4 turn off,the N-channel MOS transistors N2 and N3 turn on, loop signal current inthe opposite direction flows from the constant-current source 6 to theconstant-current source 7 via the N-channel MOS transistor N3,non-inverting output terminal 3, transmission line 44, terminatingresistor RL, transmission line 44, non-inverting output terminal 2 andN-channel MOS transistor N2, and the receiver circuit recognizes thelogic L level.

[0044] Operation according to the first embodiment will be describednext. FIG. 3 is a diagram useful in describing the operation of thetransmitter circuit according to the first embodiment in thetransmission circuit illustrated in FIG. 2. In FIG. 3, a waveform VIindicates the non-inverted input data signal applied to the inputterminal 1, a waveform V2 the edge detection signal EMP that is outputfrom the output terminal of the exclusive-OR gate 11, a waveform V3 thedifferential output voltage across the non-inverting output terminal 2and inverting output terminal 3, a waveform V4 the voltage across theterminating resistor RL, and a waveform V5 the voltage across theterminating resistor RL when signal transmission is performed by theprior-art transmitter circuit illustrated in FIG. 11.

[0045] First, when the non-inverted input data signal applied to theinput terminal 1 does not change, the edge detection signal EMP remainsat the VSS level (the logic L level) and the VDD-level (H-level) edgedetection signal EMP is not output. When the non-inverted input datasignal is at the VDD level (logic H level), therefore, loop signalcurrent flows from the constant-current source 6 to the constant-currentsource 7 via the N-channel MOS transistor N1, non-inverting outputterminal 2, transmission line 44, terminating resistor RL, transmissionline 44, inverting output terminal 3 and N-channel MOS transistor N4.When the non-inverted input data signal is at the VSS level (logic Llevel), oppositely directed loop signal current flows from theconstant-current source 6 to the constant-current source 7 via theN-channel MOS transistor N3, inverting output terminal 3, transmissionline 44, terminating resistor RL, transmission line 44, non-invertingoutput terminal 2 and N-channel MOS transistor N2. As a result, thedifferential output voltage across the non-inverting output terminal 2and inverting output terminal 3 has a voltage amplitude in the steadystate.

[0046] Next, if the non-inverted input data signal changes from the VSSlevel (logic L level) to the VDD level (logic H level), then loop signalcurrent flows from the constant-current source 6 to the constant-currentsource 7 via the N-channel MOS transistor N1, non-inverting outputterminal 2, transmission line 44, terminating resistor RL, transmissionline 44, inverting output terminal 3 and N-channel MOS transistor N4.However, the edge detecting circuit 9 detects the rising edge of thewaveform of the non-inverted input data signal and outputs the edgedetection signal EMP at the VDD level (the logic H level). As a result,the switch means 13 turns on, the current of the constant-current source12 is added to the current of the constant-current source 6, the switchmeans 16 also turns on, the current of the constant-current source 15 isadded to the current of the constant-current source 7 and the loopsignal current increases. When a time equivalent to the pulse width ofthe edge detection signal EMP elapses from the timing of the rising edgeof the waveform of the non-inverted input data signal, the switch means13 and 16 turn off again and the steady state is attained. Accordingly,the differential output voltage across the non-inverting output terminal2 and inverting output terminal 3 takes on a signal waveform whosevoltage amplitude becomes large temporarily in comparison with thesteady state for a period of time equivalent to the pulse width of theedge detection signal EMP measured from the timing of the rising edge ofthe waveform of the non-inverted input data signal.

[0047] Conversely, if the non-inverted input data signal changes fromthe VDD level (logic H level) to the VSS level (logic L level), thenoppositely directed loop signal current flows from the constant-currentsource 6 to the constant-current source 7 via the N-channel MOStransistor N3, inverting output terminal 3, transmission line 44,terminating resistor RL, transmission line 44, non-inverting outputterminal 2 and N-channel MOS transistor N2. However, the edge detectingcircuit 9 detects the falling edge of the waveform of the non-invertedinput data signal and outputs the edge detection signal EMP at the VDDlevel (the logic H level). As a result, the switch means 13 turns on,the current of the constant-current source 12 is added to the current ofthe constant-current source 6, the switch means 16 also turns on, thecurrent of the constant-current source 15 is added to the current of theconstant-current source 7 and the loop signal current increases. When atime equivalent to the pulse width of the edge detection signal EMPelapses from the timing of the falling edge of the waveform of thenon-inverted input data signal, the switch means 13 and switch means 16turn off again and the steady state is attained. Accordingly, thedifferential output voltage across the non-inverting output terminal 2and inverting output terminal 3 takes on a waveform whose voltageamplitude becomes large temporarily in comparison with the steady statefor a period of time equivalent to the pulse width of the edge detectionsignal EMP measured from the timing of the falling edge of the waveformof the non-inverted input data signal.

[0048] The pulse width of the edge detection signal EMP is set inaccordance with the relationship among the resistance value of thealuminum or copper conductor, the parasitic capacitors CO1, CO2, CI1 andCI2 and the current values of the constant-current source 12 andconstant-current source 15 in such a manner that the voltage across theterminating resistor RL will take on an excellent waveform.

[0049] Accordingly, as indicated by waveform V4 in FIG. 3, the voltageacross the terminating resistor RL becomes an excellent waveformexhibiting rapid rise and fall that follow up well the non-invertedinput data signal. By contrast, the prior-art transmitter circuitillustrated in FIG. 11 does not possess the output-waveform controlcircuit 8. Consequently, as indicated a V5 in FIG. 3, the waveformbecomes rounded or blunted and excellent signal transmission cannot beachieved.

[0050] As described above, the transmitter circuit according to thefirst embodiment of the present invention is provided with theoutput-waveform control circuit 8 and is adapted so as to increase theoutput signal amplitude temporarily from the edge of the input datasignal waveform. As a result, even if the transmission line has a highresistance component as in the case of aluminum or copper conductor on aglass substrate, blunting of the signal at the input end of the receivercircuit is reduced and it becomes possible to achieve high-speed signaltransmission.

[0051]FIG. 4 is a circuit diagram illustrating a transmitter circuitaccording to a second embodiment of the present invention. Structurally,the transmitter circuit according to the second embodiment of FIG. 4differs from the transmitter circuit according to the first embodimentof FIG. 1 only in that the output-waveform control circuit 8 is modifiedto an output-waveform control circuit 17. The two transmitter circuitsare structurally identical in all other respects. Components in FIG. 4identical with those shown in FIG. 1 are designated by like referencecharacters and need not be described again.

[0052] As shown in FIG. 4, the transmitter circuit according to thesecond embodiment includes the input terminal 1, non-inverting outputterminal 2, inverting output terminal 3, driver circuit 4 andoutput-waveform control circuit 17.

[0053] The output-waveform control circuit 17 includes CMOS-typeinverter circuits 18 and 20 and capacitors 19 and 21. The input terminalof the inverter circuit 20 is connected to the input terminal 1 and hasthe non-inverted input data signal applied thereto. One end of thecapacitor 21 is connected to the output terminal of the inverter circuit20 and the other end of the capacitor 21 is connected to the invertingoutput terminal 3. The input terminal of the inverter circuit 18 isconnected to the output terminal of the inverter circuit 5 and has theinverted input data signal applied thereto. One end of the capacitor 19is connected to the output terminal of the inverter circuit 18 and theother end of the capacitor 19 is connected to the non-inverting outputterminal 2.

[0054] The capacitor 21 differentiates the output voltage of theinverter circuit 20 and applies the resultant signal to the invertingoutput terminal 3, and the capacitor 19 differentiates the outputvoltage of the inverter circuit 18 and applies the resultant signal tothe non-inverting output terminal 2.

[0055] Operation according to the second embodiment will be describednext. FIG. 5 is a diagram useful in describing the operation of thetransmitter circuit according to the second embodiment in thetransmission circuit illustrated in FIG. 2. In FIG. 5, the waveform VIindicates the non-inverted input data signal applied to the inputterminal 1, a waveform V6 the differential output voltage across thenon-inverting output terminal 2 and inverting output terminal 3, and awaveform V7 the voltage across the terminating resistor RL.

[0056] First, when the non-inverted input data signal applied to theinput terminal 1 does not change and is at the VDD level (the logic Hlevel), loop signal current flows from the constant-current source 6 tothe constant-current source 7 via the N-channel MOS transistor N1,non-inverting output terminal 2, transmission line 44, terminatingresistor RL, transmission line 44, inverting output terminal 3 andN-channel MOS transistor N4. When the non-inverted input data signal isat the VSS level (logic L level), oppositely directed loop signalcurrent flows from the constant-current source 6 to the constant-currentsource 7 via the N-channel MOS transistor N3, inverting output terminal3, transmission line 44, terminating resistor RL, transmission line 44,non-inverting output terminal 2 and N-channel MOS transistor N2. As aresult, the differential output voltage across the non-inverting outputterminal 2 and inverting output terminal 3 has a voltage amplitude inthe steady state.

[0057] Next, if the non-inverted input data signal changes from the VSSlevel (logic L level) to the VDD level (logic H level), then loop signalcurrent flows from the constant-current source 6 to the constant-currentsource 7 via the N-channel MOS transistor N1, non-inverting outputterminal 2, transmission line 44, terminating resistor RL, transmissionline 44, inverting output terminal 3 and N-channel MOS transistor N4.However, the inverter circuit 20 detects the rising edge of the waveformof the non-inverted input data signal and a voltage that is the resultof differentiating the output voltage of the inverter circuit 20 by thecapacitor 21 is added to the voltage at the inverting output terminal 3.At the same time, the inverter circuit 18 detects the falling edge ofthe waveform of the inverted input data signal and a voltage that is theresult of differentiating the output voltage of the inverter circuit 18by the capacitor 19 is added to the voltage at the non-inverting outputterminal 2, whereby the loop signal current is increased. Accordingly,the differential output voltage across the non-inverting output terminal2 and inverting output terminal 3 takes on a waveform whose voltageamplitude becomes large temporarily in comparison with the steady statefrom the timing of the rising edge of the waveform of the non-invertedinput data signal.

[0058] Conversely, if the non-inverted input data signal changes fromthe VDD level (logic H level) to the VSS level (logic L level), thenoppositely directed loop signal current flows from the constant-currentsource 6 to the constant-current source 7 via the N-channel MOStransistor N3, inverting output terminal 3, transmission line 44,terminating resistor RL, transmission line 44, non-inverting outputterminal 2 and N-channel MOS transistor N2. However, the invertercircuit 20 detects the falling edge of the waveform of the non-invertedinput data signal and a voltage that is the result of differentiatingthe output voltage of the inverter circuit 20 by the capacitor 21 isadded to the voltage at the inverting output terminal 3. At the sametime, the inverter circuit 18 detects the rising edge of the waveform ofthe inverted input data signal and a voltage that is the result ofdifferentiating the output voltage of the inverter circuit 18 by thecapacitor 19 is added to the voltage at the non-inverting outputterminal 2, whereby the loop signal current is increased. Accordingly,the differential output voltage across the non-inverting output terminal2 and inverting output terminal 3 takes on a waveform whose voltageamplitude becomes large temporarily in comparison with the steady statefrom the timing of the falling edge of the waveform of the non-invertedinput data signal.

[0059] The capacitance values of the capacitors 19 and 21 are set inaccordance with the relationship among the resistance value of thealuminum or copper conductor and the parasitic capacitors CO1, CO2, CI1and CI2 (see FIG. 2) in such a manner that the voltage across theterminating resistor RL will take on an excellent waveform.

[0060] Accordingly, as indicated by waveform V7 in FIG. 5, the voltageacross the terminating resistor RL becomes an excellent waveformexhibiting rapid rise and fall that follow up well the non-invertedinput data signal.

[0061] In accordance with the transmitter circuit of the secondembodiment, as described above, the edge of the waveform of thenon-inverted input data signal is detected by the inverter circuit 20and a voltage that is the result of differentiating the output voltageof the inverter circuit 20 is added to the voltage at the invertingoutput terminal 3. At the same time, the edge of the non-inverted inputdata signal is detected by the inverter circuit 18 and a voltage that isthe result of differentiating the output voltage of the inverter circuit18 is added to the voltage at the non-inverting output terminal 2.Accordingly, effects similar to these of the first embodiment areobtained by circuitry of a scale smaller than that of the transmittercircuit of the first embodiment.

[0062]FIG. 6 is a circuit diagram illustrating a transmitter circuitaccording to a third embodiment of the present invention. As illustratedin FIG. 6, the transmitter circuit according to the third embodimentincludes the input terminal 1, the non-inverting output terminal 2, theinverting output terminal 3, a driver circuit 22 and an output-waveformcontrol circuit 36.

[0063] The driver circuit 22 includes a CMOS-type inverter circuit 23,potential dividing circuits 24 and 27 and switch means 25, 26, 28 and29.

[0064] The potential dividing circuit 24 has resistors R1, R2 and R3connected serially between the high-potential power supply VDD andlow-potential power supply VSS for generating a potential-dividedvoltage VH (high level) from the connection node of the resistors R1 andR2 and a potential-divided voltage VL (low level), which is lower thanthe potential-divided voltage VH, from the connection node of theresistors R2 and R3.

[0065] Similarly, the potential dividing circuit 27 has resistors R4, R5and R6 connected serially between the high-potential power supply VDDand low-potential power supply VSS for generating a potential-dividedvoltage VH (high level) from the connection node of the resistors R4 andR5 and a potential-divided voltage VL (low level), which is lower thanthe potential-divided voltage VH, from the connection node of theresistors R5 and R6.

[0066] The switch means 25 includes an N-channel MOS transistor N6 and aP-channel MOS transistor P2 and is a transfer gate obtained byconnecting the source-drain line of the N-channel MOS transistor N6 inparallel with the source-drain line of the P-channel MOS transistor P2.The potential-divided voltage VH from the potential dividing circuit 24is applied to one end of the switch means 25; the other end of theswitch means 25 is connected to the non-inverting output terminal 2.

[0067] The switch means 26 includes an N-channel MOS transistor N7 and aP-channel MOS transistor P3 and is a transfer gate obtained byconnecting the source-drain line of the N-channel MOS transistor N7 inparallel with the source-drain line of the P-channel MOS transistor P3.The potential-divided voltage VL from the potential dividing circuit 24is applied to one end of the switch means 26; the other end of theswitch means 26 is connected to the non-inverting output terminal 2.

[0068] The input terminal 1 is connected to the gate terminal of theN-channel MOS transistor N6, the gate terminal of the P-channel MOStransistor P3 and the input terminal of the inverter circuit 23. Theoutput terminal of the inverter circuit 23 is connected to the gateterminal of the P-channel MOS transistor P1 and to the gate terminal ofthe N-channel MOS transistor N7. The switch means 25 and 26 select thepotential-divided voltage VH and output it to the non-inverting outputterminal 2 when the CMOS-level non-inverted input data signal thatenters the input terminal 1 is at the VDD level (the logic H level), andselect the potential-divided voltage VL and output it to thenon-inverting output terminal 2 when the non-inverted input data is atthe VSS level (the logic L level).

[0069] The switch means 28 includes an N-channel MOS transistor N8 and aP-channel MOS transistor P4 and is a transfer gate obtained byconnecting the source-drain line of the N-channel MOS transistor N8 inparallel with the source-drain line of the P-channel MOS transistor P4.The potential-divided voltage VH from the potential dividing circuit 27is applied to one end of the switch means 28; the other end of theswitch means 28 is connected to the inverting output terminal 3.

[0070] The switch means 29 includes an N-channel MOS transistor N9 and aP-channel MOS transistor P5 and is a transfer gate obtained byconnecting the source-drain line of the N-channel MOS transistor N8 inparallel with the source-drain line of the P-channel MOS transistor P5.The potential-divided voltage VL from the potential dividing circuit 27is applied to one end of the switch means 29; the other end of theswitch means 28 is connected to the inverting output terminal 3.

[0071] The input terminal 1 is connected to the gate terminal of theP-channel MOS transistor P4 and to the gate terminal of the N-channelMOS transistor N9, and the output terminal of the inverter circuit 23 isconnected to the gate terminal of the N-channel MOS transistor N8 and tothe gate terminal of the P-channel MOS transistor P5. The switch means28 and 29 select the potential-divided voltage VL and output it to theinverting output terminal 3 when the CMOS-level non-inverted input datasignal that enters the input terminal 1 is at the VDD level (the logic Hlevel), and select the potential-divided voltage VH and output it to theinverting output terminal 3 when the non-inverted input data is at theVSS level (the logic L level).

[0072] The output-waveform control circuit 36 includes an edge detectingcircuit 30 and switch means 37, 39, 40 and 42.

[0073] The edge detecting circuit 30 includes a CMOS-type non-invertingbuffer circuit 31, a CMOS-type exclusive-OR gate 32, a CMOS-typeinverter circuit 33 and CMOS-type AND gates 34 and 35. An input terminalof the non-inverting buffer circuit 31, a first input terminal of theexclusive-OR gate 32, the input terminal of the inverter circuit 33 anda first input terminal of the AND gate 34 are tied together andconnected to the input terminal 1 as the input terminal of the edgedetecting circuit 30. The output terminal of the non-inverting buffercircuit 31 is connected to a second input terminal of the exclusive-ORgate 32. The output terminal of the exclusive-OR gate 32 is connected toa second input terminal of the AND gate 34 and to a second inputterminal of the AND gate 35. The output terminal of the inverter circuit33 is connected to a first input terminal of the AND gate 35. The edgedetecting circuit 30 detects the rising edge of the waveform of thenon-inverted input data signal that enters the input terminal 1, therebyoutputting the edge detection signal EMP (UP) from the output terminalof the AND gate 34. The edge detecting circuit 30 detects the fallingedge of the waveform of the non-inverted input data signal, therebyoutputting the edge detection signal EMP (DN) from the output terminalof the AND gate 35. The pulse width of the edge detection signals EMP(UP) and EMP (DN) is equal to the delay time of the non-inverting buffercircuit 31. This delay time can be set appropriately. If thenon-inverting buffer circuit 31 is constructed from an even-number ofinverter circuit stages, then the delay time can be changed by changingthe number of stages that operate.

[0074] The switch means 37 includes a CMOS-type inverter circuit 38 anda P-channel MOS transistor P6. The source terminal of the P-channel MOStransistor P6 is connected to the high-potential power supply VDD, thedrain terminal of the P-channel MOS transistor P6 is connected to theinverting output terminal 3, the gate terminal of the P-channel MOStransistor P6 is connected to the output terminal of the invertercircuit 38, and the input terminal of the inverter circuit 38 isconnected to the output terminal of the AND gate 35. The P-channel MOStransistor P6 is turned on when the edge detection signal EMP (DN) atthe VDD level (the logic H level) is input, thereby pulling up theinverting output terminal 3 toward the high-potential power supply VDD.

[0075] The switch means 40 includes a CMOS-type inverter circuit 41 anda P-channel MOS transistor P7. The source terminal of the P-channel MOStransistor P7 is connected to the high-potential power supply VDD, thedrain terminal of the P-channel MOS transistor P7 is connected to thenon-inverting output terminal 2, the gate terminal of the P-channel MOStransistor P7 is connected to the output terminal of the invertercircuit 41, and the input terminal of the inverter circuit 41 isconnected to the output terminal of the AND gate 34. The P-channel MOStransistor P7 is turned on when the edge detection signal EMP (UP) atthe VDD level (the logic H level) is input, thereby pulling up thenon-inverting output terminal 2 toward the high-potential power supplyVDD.

[0076] The source of an N-channel MOS transistor N10 serving as switchmeans 39 is connected to the low-potential power supply VSS, the drainof the N-channel MOS transistor N10 is connected to the inverting outputterminal 3, and the gate terminal of the N-channel MOS transistor N10 isconnected to the output terminal of the AND gate 34. The N-channel MOStransistor N10 is turned on when the edge detection signal EMP (UP) atthe VDD level (the logic H level) is input, thereby pulling down theinverting output terminal 3 toward the low-potential power supply VSS.

[0077] The source of an N-channel MOS transistor N11 serving as switchmeans 42 is connected to the low-potential power supply VSS, the drainof the N-channel MOS transistor N11 is connected to the non-invertingoutput terminal 2, and the gate terminal of the N-channel MOS transistorN11 is connected to the output terminal of the AND gate 35. TheN-channel MOS transistor N11 is turned on when the edge detection signalEMP (DN) at the VDD level (the logic H level) is input, thereby pullingdown the non-inverting output terminal 2 toward the low-potential powersupply VSS.

[0078] Operation according to the third embodiment will be describednext. FIG. 7 is a diagram useful in describing the operation of thetransmitter circuit according to the third embodiment in thetransmission circuit illustrated in FIG. 2. In FIG. 7, waveform VIindicates the non-inverted input data signal applied to the inputterminal 1, a waveform V8 the edge detection signal EMP (UP) that isoutput from the output terminal of the AND gate 34, a waveform V9 theedge detection signal EMP (DN) that is output from the output terminalof the AND gate 35, a waveform V11 the differential output voltageacross the non-inverting output terminal 2 and inverting output terminal3, and a waveform V11 the voltage across the terminating resistor RL.

[0079] First, when the non-inverted input data signal applied to theinput terminal 1 does not change, the edge detection signal EMP (UP) andthe edge detection signal EMP (DN) remain at the VSS level (the logic Llevel) and the VDD-level (H-level) edge detection signal EMP (UP) oredge detection signal EMP (DN) is not output. When the non-invertedinput data signal is at the VDD level (logic H level), therefore, thepotential-divided voltage VH is output to the non-inverting outputterminal 2 and the potential-divided voltage VL is output to theinverting output terminal 3. Accordingly, loop signal current flows fromthe non-inverting output terminal 2 to the inverting output terminal 3via the transmission line 44, terminating resistor RL and transmissionline 44. When the non-inverted input data signal is at the VSS level(logic L level), the potential-divided voltage VH is output to theinverting output terminal 3 and the potential-divided voltage VL isoutput to the non-inverting output terminal 2. Accordingly, loop signalcurrent flows from the inverting output terminal 3 to the non-invertingoutput terminal 2 via the transmission line 44, terminating resistor RLand transmission line 44. As a result, the differential output voltageacross the non-inverting output terminal 2 and inverting output terminal3 has a voltage amplitude in the steady state.

[0080] Next, if the non-inverted input data signal changes from the VSSlevel (logic L level) to the VDD level (logic H level), thepotential-divided voltage VH is output to the non-inverting outputterminal 2 and the potential-divided voltage VL is output to theinverting output terminal 3. Accordingly, loop signal current flows fromthe non-inverting output terminal 2 to the inverting output terminal 3via the transmission line 44, terminating resistor RL and transmissionline 44. However, the edge detecting circuit 30 detects the rising edgeof the waveform of the non-inverted input data signal and outputs theVDD-level (logic H level) edge detection signal EMP (UP). As a result,the switch means 39 turns on and the inverting output terminal 3 ispulled down. Further, the switch means 40 also turns on and thenon-inverting output terminal 2 is pulled up. Hence the differentialoutput voltage across the non-inverting output terminal 2 and invertingoutput terminal 3 increases, thereby increasing the loop signal current.When a time equivalent to the pulse width of the edge detection signalEMP (UP) elapses from the timing of the rising edge of the waveform ofthe non-inverted input data signal, the switch means 39 and 40 turn offagain and the steady state is attained. Accordingly, the differentialoutput voltage across the non-inverting output terminal 2 and invertingoutput terminal 3 takes on a signal waveform whose voltage amplitudebecomes large temporarily in comparison with the steady state for aperiod of time equivalent to the pulse width of the edge detectionsignal EMP (UP) measured from the timing of the rising edge of thewaveform of the non-inverted input data signal.

[0081] Conversely, if the non-inverted input data signal changes fromthe VDD level (logic H level) to the VSS level (logic L level), then thepotential-divided voltage VH is output to the inverting output terminal3 and the potential-divided voltage VL is output to the non-invertingoutput terminal 2. Accordingly, loop signal current flows from theinverting output terminal 3 to the non-inverting output terminal 2 viathe transmission line 44, terminating resistor RL and transmission line44. However, the edge detecting circuit 30 detects the falling edge ofthe waveform of the non-inverted input data signal and outputs theVDD-level (logic H level) edge detection signal EMP (DN). As a result,the switch means 39 turns on and the inverting output terminal 3 ispulled up. Further, the switch means 42 also turns on and thenon-inverting output terminal 2 is pulled down. Hence the differentialoutput voltage across the non-inverting output terminal 2 and invertingoutput terminal 3 increases, thereby increasing the loop signal current.When a time equivalent to the pulse width of the edge detection signalEMP (DN) elapses from the timing of the falling edge of the waveform ofthe non-inverted input data signal, the switch means 37 and 42 turn offagain and the steady state is attained. Accordingly, the differentialoutput voltage across the non-inverting output terminal 2 and invertingoutput terminal 3 takes on a signal waveform whose voltage amplitudebecomes large temporarily in comparison with the steady state for aperiod of time equivalent to the pulse width of the edge detectionsignal EMP (DN) measured from the timing of the falling edge of thewaveform of the non-inverted input data signal.

[0082] The pulse width of the edge detection signals EMP (UP) and EMP(DN) is set in accordance with the relationship among the resistancevalue of the aluminum or copper conductor, and the parasitic capacitorsCO1, CO2, CI1 and CI2 in such a manner that the voltage across theterminating resistor RL will take on an excellent waveform.

[0083] Accordingly, as indicated by waveform V11 in FIG. 7, the voltageacross the terminating resistor RL becomes an excellent waveformexhibiting rapid rise and fall that follow up well the non-invertedinput data signal.

[0084] It should be noted that since the transmitter circuit accordingto this embodiment is of the voltage-output type, signal transmissionbased upon a differential voltage signal rather than a loop current canbe achieved without connecting the terminating resistor RL.

[0085] In accordance with the transmitter circuit according to the thirdembodiment of the invention, as described above, effects similar tothose of the transmitter circuit of the first embodiment are obtained.Since the transmitter circuit is of the voltage-output type, signaltransmission can be performed without connecting the terminatingresistor RL and a further effect obtained is that a limitation ondynamic range can be reduced.

[0086]FIG. 8 is a circuit diagram illustrating a transmitter circuitaccording to a fourth embodiment of the present invention. Structurally,the transmitter circuit according to the fourth embodiment of FIG. 8differs from the transmitter circuit according to the third embodimentof FIG. 6 only in that the output-waveform control circuit 36 in thetransmitter circuit of the third embodiment shown in FIG. 6 is replacedwith the output-waveform control circuit 17 of the transmitter circuitaccording to the second embodiment shown in FIG. 4. The two transmittercircuits are structurally identical in all other respects. Components inFIG. 8 identical with those shown in FIGS. 4 and 6 are designated bylike reference characters and need not be described again.

[0087] As shown in FIG. 8, the transmitter circuit according to thefourth embodiment includes the input terminal 1, non-inverting outputterminal 2, inverting output terminal 3, driver circuit 22 andoutput-waveform control circuit 17.

[0088] In accordance with the transmitter circuit of the fourthembodiment, as described above, effects similar to these of the thirdembodiment are obtained by circuitry of a scale smaller than that of thetransmitter circuit of the third embodiment.

[0089]FIG. 9 is a block diagram of driver units according to a fifthembodiment of the present invention. Specifically, two source driver LSIchips 46 serving as the driver units according to this embodiment areconnected in cascade. Further, FIG. 10 is a diagram illustrating thestructure of a matrix display panel having driver units according tothis embodiment. As illustrated in FIG. 10, a timing controller LSI chip51 and a plurality of source driver LSI chips 46 are mounted directly ona glass substrate 50 of a matrix display panel of a TFT liquid crystaldevice, organic EL display device or plasma display device. The timingcontroller LSI chip 51 and the source driver LSI chips 46 performtransmission of grayscale data signals, and the plurality of sourcedriver LSI chips 46 perform transmission of grayscale data signals incascade. Transmission is via a transmission line consisting of aluminumor copper conductor formed on the glass substrate 50 by themanufacturing process of the matrix display panel. If the matrix displaypanel has, e.g., 1024 columns, then eight of the source driver LSI chips46 each having 128 columns would be connected in cascade.

[0090] As shown in FIG. 9, each source driver LSI chip 46 includes thetransmitter circuit 43, the receiver circuit 45, a shift register 47, alatch circuit 48 and a data-line driver circuit 49. The transmittercircuit 43 is any one of the transmitter circuit of the first embodimentshown in FIG. 1, the transmitter circuit of the second embodiment shownin FIG. 4, the transmitter circuit of the third embodiment shown in FIG.6 or the transmitter circuit of the fourth embodiment shown in FIG. 8.Further, the transmitter circuit 43, receiver circuit 45 and thetransmission line 44 between the transmitter circuit 43 and the receivercircuit 45 constitute the transmission circuit shown in FIG. 2. Thetransmission line 44 connected to the input terminal of the receivercircuit 45 from the preceding stage, the output terminal of the receivercircuit 45 is connected to the serial input terminal of the shiftregister 47, and the serial output terminal of the shift register 47 isconnected to the input terminal 1 of the transmitter circuit 43.

[0091] When the timing controller LSI chip 51 stores one frame of imagedata in a frame memory, the timing controller LSI chip 51 successivelyinputs one horizontal line of grayscale data, which is for driving adata line of the matrix display panel, to cascade-connected shiftregisters 47 via the transmitter circuit 43, transmission line 44 andreceiver circuit 45 while applying a shift clock to each of the sourcedriver LSI chips 46. When 128 columns of grayscale data is stored in theshift register 47, the grayscale data is transferred to the latchcircuit 48 in response to a control signal from the timing controllerLSI chip 51. Furthermore, analog driving voltage corresponding to thegrayscale data held in the latch circuit 48 is sent from the data-linedriver circuit 49 to the data line (source line of the TFT) of thematrix display panel, whereby a display is presented.

[0092] In accordance with the drive unit of the fifth embodiment, asdescribed above, the drive unit is provided with the transmitter circuit43 connected to the serial output terminal of one shift register 47, andthe receiver circuit 45 connected to the serial input terminal of theother shift register 47. As a result, even though the source driver LSIchips 46 and timing controller LSI chip 51 are mounted on the glasssubstrate 50 of the matrix display panel and signal transmission isperformed by high-resistance aluminum or copper conductor formed on theglass substrate 50, blunting or rounding of the signal waveform at theinput terminal of the receiver circuit 45 is reduced, thereby making itpossible to perform high-speed transmission of a grayscale data signal.

[0093] It should be noted that although the driver circuit in thetransmitter circuit according to the first and second embodiments reliesupon N-channel MOS transistors, these can be replaced with P-channel MOStransistors.

[0094] Further, the non-inverting buffer for delay in the transmittercircuit according to the first and third embodiments may be adapted soas to latch the non-inverted input data signal by a delay clock.

[0095] The meritorious effects of the present invention are summarizedas follows.

[0096] The effect of the present invention is that it is possible toimplement a transmitter circuit, transmission circuit and driver unit inwhich even if a transmission line has a high resistance component, as isthe case with aluminum or copper conductor formed on a glass substrate,blunting or rounding of the signal waveform at the input terminal of thereceiver circuit is reduced, thereby making it possible to performhigh-speed signal transmission.

[0097] As many apparently widely different embodiments of the presentinvention can be made without departing from the spirit and scopethereof, it is to be understood that the invention is not limited to thespecific embodiments thereof except as defined in the appended claims.

[0098] It should be noted that other objects, features and aspects ofthe present invention will become apparent in the entire disclosure andthat modifications may be done without departing the gist and scope ofthe present invention as disclosed herein and claimed as appendedherewith.

[0099] Also it should be noted that any combination of the disclosedand/or claimed elements, matters and/or items may fall under themodifications aforementioned.

What is claimed is:
 1. A transmitter circuit comprising: a drivercircuit having a non-inverting output terminal and an inverting outputterminal for outputting a signal current, which has a loop directionthat changes based upon an input signal, to the non-inverting outputterminal and inverting output terminal; and an output-waveform controlcircuit for detecting a waveform edge of the input signal and respondingby increasing the signal current temporarily.
 2. The transmitter circuitaccording to claim 1, wherein said output-waveform control circuitincludes: an edge detecting circuit receiving the input signal andoutputting a detection signal when the edge of the input signal isdetected; switch means controlled to be turned on by the detectionsignal; and a current source for supplying a current, which is added tothe signal current, when said switch means has been turned on.
 3. Thetransmitter circuit according to claim 1, wherein said output-waveformcontrol circuit includes: a first inverter circuit receiving anon-inverted input signal; a first capacitor having one end connected toan output terminal of said first inverter circuit and another endconnected to the inverting output terminal; a second inverter circuitreceiving an inverted input signal; and a second capacitor having oneend connected to an output terminal of the second inverter circuit andanother end connected to the non-inverting output terminal.
 4. Thetransmitter circuit according to claim 1, wherein said driver circuitincludes: a non-inverting output terminal and an inverting outputterminal; a first transistor for receiving a non-inverted input signaland switching in response to pass a current from a high-potential powersupply to the non-inverting output terminal; a second transistor forreceiving an inverted input signal and switching in response to pass acurrent from the non-inverting output terminal to the low-potentialpower supply; a third transistor for receiving the inverted inputsignal, and switching in response to pass a current from thehigh-potential power supply to the inverting output terminal; and afourth transistor for receiving the non-inverted input signal andswitching on in response to pass a current from the inverting outputterminal to a low-potential power supply.
 5. A transmitter circuitcomprising: a driver circuit, which has a non-inverting output terminaland an inverting output terminal, for outputting a differential voltage,whose polarity changes based upon an input signal, to the non-invertingoutput terminal and inverting output terminal; and an output-waveformcontrol circuit for detecting a waveform edge of the input signal andresponding by increasing the differential voltage temporarily.
 6. Thetransmitter circuit according to claim 5, wherein said output-waveformcontrol circuit includes: an edge detecting circuit for outputting afirst detection signal when a rising edge of the waveform is detectedand a second detection signal when a falling edge of the waveform isdetected; a first switch circuit for pulling up the non-inverting outputterminal in response to the first detection signal; a second switchcircuit for pulling down the inverting output terminal in response tothe first detection signal; a third switch circuit for pulling down thenon-inverting output terminal in response to the second detectionsignal; and a fourth switch circuit for pulling up the inverting outputterminal in response to the second detection signal.
 7. The transmittercircuit according to claim 5, wherein said driver circuit includes: apotential dividing circuit for generating high- and low-levelpotential-divided voltages; a first switch circuit for selecting thepotential-divided voltage based upon a non-inverted input signal andoutputting the voltage to the non-inverting output terminal; and asecond switch circuit for selecting the potential-divided voltage basedupon the non-inverted input signal and outputting the voltage to theinverting output terminal.
 8. A transmission circuit comprising: thetransmitter circuit as set forth in claim 1; a transmission line havingone end connected to the non-inverting output terminal and invertingoutput terminal of said transmitter circuit; and a receiver circuitconnected to the other end of said transmission line.
 9. A driver unitcomprising: a shift register circuit receiving grayscale data fordriving data lines of a matrix display panel; and the transmittercircuit as set forth in claim 1, connected to a serial output end ofsaid shift register circuit.
 10. The driver unit according to claim 9,further comprising the transmission line having one end connected to thenon-inverting output terminal and inverting output terminal of saidtransmitter circuit.
 11. The driver unit according to claim 10, whereinsaid transmission line comprises a conductor on a glass substrate of thematrix display panel.
 12. A transmission circuit comprising: thetransmitter circuit as set forth in claim 5; a transmission line havingone end connected to the non-inverting output terminal and invertingoutput terminal of said transmitter circuit; and a receiver circuitconnected to the other end of said transmission line.
 13. A driver unitcomprising: a shift register circuit receiving grayscale data fordriving data lines of a matrix display panel; and the transmittercircuit as set forth in claim 5, connected to a serial output end ofsaid shift register circuit.
 14. The driver unit according to claim 13,further comprising the transmission line having one end connected to thenon-inverting output terminal and inverting output terminal of saidtransmitter circuit.
 15. The driver unit according to claim 14, whereinsaid transmission line comprises a conductor on a glass substrate of thematrix display panel.
 16. A transmitter circuit comprising: a drivercircuit including an input terminal for receiving an input signal; apair of differential output terminals for outputting a differentialoutput signal; and first and second current sources for supplying sourceand sink currents; said driver circuit responsive to the input signalreceived at the input terminal performing control so that charging driveof one of said differential output terminals with the source current anddischarging drive of the other of said differential output terminalswith the sink current are performed; an edge detection circuit receivingthe input signal and detecting a transition of the input signal tooutput a detection signal which is set in an active state for a presetperiod; and third and fourth current sources, both receiving thedetection signal from the edge detection circuit and controlled to beset into an active state when the detection signal is set in an activestate to provide respective currents which are summed to saidsource/sink currents from said first and second currents sources; saidthird and forth current sources being controlled to be in an inactivestate when the detection signal is set in an inactive state.
 17. Atransmitter circuit comprising: a driver circuit having an inputterminal for receiving an input signal and a pair of differential outputterminals for outputting a differential output signal and controlling,responsive to the input signal received at the input terminal, so as toperform charging drive of one of said differential output terminals anddischarging drive of the other of said differential output terminals;and first and second differentiators receiving the input signal and acomplementary signal of the input signal respectively and havingrespective outputs connected to said differential output terminals;wherein when the input signal undergoes a transition, the differentialoutput signal from said differential output terminals has a waveformhaving an amplitude thereof increased temporally by the outputs fromsaid first and second differentiators.
 18. A transmitter circuitcomprising: a driver circuit including: an input terminal for receivingan input signal; a pair of differential output terminals for outputtinga differential output signal; a first voltage divider circuit includinga plurality of resistors serially connected across first and secondpower supplies and outputting first and second voltages from first andsecond connection nodes of said resistors; a first selector circuitreceiving respective voltages from said first and second connectionnodes of said first voltage divider circuit and selecting one of thereceived two voltages based on the input signal received at the inputterminal to supply so selected voltage to a first terminal constitutingsaid differential output terminals; a second voltage divider circuitincluding a plurality of resistors serially connected across said firstand second power supplies and outputting first and second voltages fromfirst and second connection nodes of said resistors; and a secondselector circuit receiving respective voltages from said first andsecond connection nodes of said second voltage divider circuit andselecting one of the received two voltages, which is complementary tothe voltage supplied to the first terminal of said differential outputterminals, based on said input signal to supply so selected voltage to asecond terminal constituting said differential output terminals; an edgedetection circuit receiving the input signal and detecting rise and falltransitions of the input signal to output respectively first and seconddetection signals which are set in an active state for a preset period;and a control circuit having two outputs respectively connected to saiddifferential output terminals, receiving said first and second detectionsignals from the edge detection circuit and performing control so thatcharging drive of the first terminal of said differential outputterminals and discharging drive of the second terminal of saiddifferential output terminals are performed concurrently when the firstdetection signal is in an active state, while charging drive of thesecond terminal of said differential output terminals and dischargingdrive of the first terminal of said differential output terminals areperformed concurrently when the second detection signal is in an activestate.
 19. A transmitter circuit comprising: a driver circuit including:an input terminal for receiving an input signal; a pair of differentialoutput terminals for outputting a differential output signal; a firstvoltage divider circuit including a plurality of resistors seriallyconnected across first and second power supplies and outputting firstand second voltages from first and second connection nodes of saidresistors; a first selector circuit receiving respective voltages fromsaid first and second connection nodes of said first voltage dividercircuit and selecting one of the received two voltages based on theinput signal received at the input terminal to supply so selectedvoltage to a first terminal constituting said differential outputterminals; a second voltage divider circuit including a plurality ofresistors serially connected across said first and second power suppliesand outputting first and second voltages from first and secondconnection nodes of said resistors; and a second selector circuitreceiving respective voltages from said first and second connectionnodes of said second voltage divider circuit and selecting one of thereceived two voltages, which is complementary to the voltage supplied tothe first terminal of said differential output terminals, based on saidinput signal to supply so selected voltage to a second terminalconstituting said differential output terminals; and first and seconddifferentiators receiving said input signal and a complementary signalof said input signal respectively and having respective outputsconnected to said differential output terminals; wherein when the inputsignal undergoes a transition, the differential output signal from saiddifferential output terminals has a waveform having an amplitude thereofincreased temporally by the outputs from said first and seconddifferentiators.
 20. The transmitter circuit according to claim 16,wherein said driver circuit includes: a first series circuit comprisingfirst and second transistors serially connected across said firstcurrent source and said second current source; said first and secondtransistors having control terminals for receiving the input signal andan inverted signal obtained by inverting the input signal respectivelywith a connection node of said first and second transistors beingconnected to a first terminal constituting said differential outputterminals; and a second series circuit comprising third and fourthtransistors serially connected in parallel with said first seriescircuit across said first current source and said second current source;said third and fourth transistors having control terminals for receivingthe inverted signal and the input signal respectively with a connectionnode of said third and fourth transistors being connected to a secondterminal constituting said differential output terminals.